The compiler is self-hosted: it is written in Silica, builds itself, and runs the trials. Work is organised by emitter path and delivered in chunks between fixed points; the authoritative checklist is the roadmap. How to open issues and PRs is in CONTRIBUTING.md. The code organization document helps you navigate the tree, and Build and test the compiler explains how to build for every platform, for some of them, or for just the machine you are on, and covers the trials and the fixed-point check.

Fixed points and chunks

A fixed point is a self-hosted compiler that passes the whole trial tree when built by itself and then reproduces itself byte for byte (make fixpoint). A chunk is a slice of the not-yet-implemented specification; it is closed by the next fixed point on that path, never by a build that merely compiles. Every chunk ships with trials.

Paths still in progress

Apple Silicon, Linux AArch64 and Linux x86-64 are working hosted paths, each with its own fixed point, and the chunks below are taken up on them in lock-step (Apple Silicon leads inside a chunk). What is still being built is the bare-metal side:

  • ESP32-S3 (Xtensa LX7, OS-free) is not in lock-step, and it has no fixed point: the board cannot host a compiler, so it can never build itself. Its milestone is a board release, every trial suite green on the board from a cross compiler built on a hosted machine. Its first board release has all the behaviours of the hosted first fixed point plus peek and poke — map_device binding a board-legal MMIO window, and the dedicated peek and poke prims for volatile device loads and stores, callable only from a spawn_device worker. They name registers, not offsets, and every access is checked against a device description the programmer supplies. The lexer through the SIR generator are shared by every path, so the hosted paths take the same change at that point, with their emitters rejecting the prims as a compile error, and re-establish their fixed points. After that first board release, ESP32-S3 works through the same chunks at its own pace, skipping hosted-only items. The board has not received a new compiler since the hosted carrier work: the open items are recorded as the “ESP32-S3 board gap” in the roadmap; the work is on a separate branch. Port notes: esp32s3_xtensa_port.md, porting_for_os_free_targets.md, device actor specification.

Raw chip features in chunk 14

Chunk 14 is the rest of the chip’s capabilities, and it is raw paths only, wherever the chip has them; a feature the chip lacks is recorded in the port notes as not applicable rather than left open. Hosted paths are different by specification: on an OS the memory spaces are a discipline without guaranteed attribute differentiation (§12.1.1.0).

Feature (spec wording) Where What the raw path delivers
Memory spaces. region(L, Space) with normal, normal_writeback, normal_writethrough, normal_noncacheable, atomic, and device (§4.4); OS-free runtimes give each space its real attributes, on AArch64 through MAIR_EL1 (§12.1.1.0, §12.1.1.1). §4.4, §12.1.1 Every space the chip can distinguish maps to the matching cache policy, shareability, or device attribute; device is the peek-and-poke window. Spaces the chip cannot distinguish are documented as collapsed.
Chip-specific behaviours. Feature detection and capability queries (§21.0), then whatever the chip has: on AArch64 SVE (§21.1), NEON (§21.2), MTE (§21.3), PAC (§21.4) and the system-register access of §21.0.2; on ESP32-S3 the Xtensa LX7 equivalents (its vector and cache-control instructions) and none of the AArch64-only items. §21 Each raw path carries the §21 items its chip supports, with trials, and lists the rest as not applicable.

Where you can help, by chunk

The chunks are enhancement requests, not an ordered list: the numbers are identifiers, not a sequence or a priority, and any of them can be taken up, alone or alongside others, when there is a contributor or a need. Chunks that were completed are not listed; their numbers are kept so references stay stable. Each chunk, whenever it is done, ends in the path’s next fixed point.

  1. Remaining standard data structures — the public traits and graph query backends not yet built (CSR and dense graph indexes, BinaryTree backends). The growable actor stacks of this chunk are delivered. Designs.
  2. Actor placement: what remains — the hosted carrier model is delivered on every hosted path. Still open: the ESP32-S3 board gap (acquire mode 2 row-child drain protection, board trials for the supervisor self-check pieces that were written but never run, and a new board compiler; see the roadmap; separate branch), and the held Linux get_actor_memory_usage and x86-64 timing measurements.
  3. Region memory safety: static lifetime analysis, buffer bounds, isolation, an ownership-based release strategy, atomic references, lifetime polymorphism. The earlier plan to make the 1,152 standard-library records with a region field linear was withdrawn after measurement: they hold only never-freed family arenas, not owned regions. The design splits owned regions (linear) from structure storage (today the never-freed family arena, spelled arena(L, S): current implementation, replaced by chunk 15 (see data_structure_redesign_requirements.md, the standard for the structure model); counted regions were rejected by Lee on 2026-10-22, Q2 a), adds a region checker and drop-based release, and copies messages between actors by default and moves them on request. Status 2026-10-23: run-time bounds checking is done on all four targets; stage 0 (H1, H3, H4, H5) and the Q9 actor-failure outcome are implemented and verified on the Mac and built on pix (linux_aarch64, compiler 999964) and nix (linux_x86_64) with no compile errors; no trials have been run on the Linux compilers yet and the ESP32-S3 mirror is not built; the rest is designed (staged 0 to 8; there is no stage 6) and not built. Messages copy by default and move only on request (Q18): the copy-on-send mechanism and the move(x) marker are in stage 4 (a language change), the narrowed E2301 in stage 5. Q1, Q2, Q3, Q4, Q5, Q7, Q8, Q9, Q10, Q11, Q13, Q14, Q15, Q16, Q17 and Q18 are decided (Q13: reading a stored inner version returns a structural copy; its copy destination and spelling are still open); Q14: a supervised child’s spec may hold a structure version, and the child receives a copy at every start and restart, released when it dies. Open details with Lee: the copy needs a child-owned region (not the never-freed family arena) and its type spelling is undecided, the cost is O(size) per restart, who makes the copy (supervisor or runtime) is undecided, and whether Q2 (a) needs a per-instance exception. Design, Region TODO.
  4. Variants and advanced control: variant types and patterns, behaviour switching, advanced effects (spec §4.2.5, §6).
  5. Atomic operations and synchronization guarantees audited and completed (spec §17, §18).
  6. Extended numerics: big integers, big floats, rationals, big rationals, and 128-bit integers as distinct explicit types with no implicit widening.
  7. Tooling and proof: formal verification, cryptographic guardrails, IDE and developer experience (spec §29), and tighter AArch64 emission without weakening the trials’ contract with checked-in baselines.
  8. Networking through Fifi: networking is not part of the language (spec §20.4); a program reaches the host’s sockets, TCP and UDP through the Foreign Function Interface (spec §26.3) like any other foreign library, inside guarded regions in dangerous actors. This chunk is the Fifi wrapper library for the host socket interface and its trials on the hosted paths. No TCP/IP stack is written. Needs the buffer bounds checking from chunk 4.
  9. Actor identity and lifecycle: the 64-bit actor identity with equality and order, the ending paths (stop_self, fail_self, kill_abnormal, orderly supervisor shutdown), supervisor report sinks, and the atom-keyed registry. Open: stop_self, fail_self and panic; supervisor :terminate_actor and :set_report_sink; the registry calls register, whereis and unregister.
  10. Time and scheduling refinement: the clocks, send_after, cancel_timer and call_with_timeout, priority hints and fairness refinement. Not started (status 2026-10-16).
  11. State-machine actors: the StateMachine trait, named states, inserted and postponed events, and the three timeout kinds. Needs the timers of chunk 11.
  12. Foreign data: byte buffers and re-creation across the Fifi boundary, with the Recreatable trait. Needs the buffer bounds checking of chunk 4.
  13. Raw paths: chip features: the memory spaces with their real attributes and the chip’s §21 behaviours. Raw paths only, and it needs peek and poke, which define the device space.
  14. Data structure redesign: ownership, copy and release of the standard structures: the standard data structures are redesigned so their memory can be copied and freed under the region ownership rules (Lee, 2026-10-23). Design needed first; a prerequisite for chunk 4 stage 2. Designs.

CI trial edge-case additions are welcome at any time: grow trials/ with scenarios that stress parsing, types, effects, and codegen so the trial tree keeps catching regressions.

Next development set: region safety for Project BEES

Decided by Lee on 2026-10-22: the next development set is region safety for Project BEES, a subset of chunk 4 ordered by what BEES needs first. Status as of 2026-10-23: items 1 to 5 (H1, H3, H4, H5, Q9/stage 8) are implemented and verified on the Mac (Apple Silicon) and built on pix (linux_aarch64, compiler 999964) and nix (linux_x86_64, build dir) with no compile errors; no trials have been run on the Linux compilers yet, the ESP32-S3 mirror is not built, and board verification is not done. The staged hazard trials are in trials/region_hazards_open_addition. Item 0 is as recorded below; item 6 is not started. Items 1 to 5 need no open decision. Item 6 rests on decisions Lee made on 2026-10-22 in the design: Q2 (a), the never-freed family arena with the atomic bump (stage 0), so counted storage, biased counting and the counted-storage stage 6 are removed from the plan; Q1 (a), the handle spelled arena(L, S); Q5 (a), a per-actor runtime owner list. Stages 2, 3, 4 and 5 remain; there is no stage 6. In the current implementation, replaced by chunk 15 (see data_structure_redesign_requirements.md), structures never reclaim memory: a 1,000-key map exhausts the ESP32-S3 heap in about 740 updates and a busy host grows by tens of MB a second.

  1. Port, check and fix the four BEES defect repros in project-bees/trials/silica_defects/: sd7_message_region_never_freed, sd20_region_tuple_return_in_actor, sd21_aggregate_return_leaks_stack and sd22_region_bound_locally_freed_after_cast. They were written 2026-09-17 and no longer compile: spawn needs a stack_policy argument, spawning before register_failure_reporter is E2236, and region_bound_locally_cast (the old sd22) needs the tagged_term helper module. Port each to current syntax, run it on today’s compiler, and record which still fail. SD-22 is design hazard H2 (stage 0). SD-7 needs the message-move machinery (design §18) and drop-based release (stage 4). SD-20 and SD-21 are probably fixed by the 2026-10-12 result-slot work; if they pass they stay as regression trials. Fixes for the ones that fail follow. Ported 2026-10-22; now trials (Mac compiler 999943). trials/message_regions_addition: SD-20 passes and is covered by the existing trial trials/memory_region_addition/region_tuple_return_in_actor, so its ported duplicate was dropped; aggregate_return_does_not_leak_stack passes and stays, because it adds a real stack leak check (the actor’s stack high_water must not grow) beyond actors_addition/aggregate_return_in_actor_keeps_stack, which detects only the fault; region_bound_locally_cast passes (prints 123) with a caveat: its region reaches the cast inside a record, which is never released (H9), so the pass may be due to that leak. SD-7 has two trials (staged in trials/message_regions_open_addition until 2026-10-22, now gated in trials/message_regions_addition; the returned-record leak below stays in the open suite, INTEGRATE_PENDING, kept out of tree runs). message_region_released is the realistic burst shape (main casts 100,000 region-carrying messages at once); its peak RSS includes the queued messages, each legitimately holding a live ~4 KB region, so it cannot tell a leak from a full queue and checks output only (~545 MB on 999943, still ~382 MiB with the SD-7 fix, the queue). message_region_released_in_flight (added 2026-10-22) keeps one message in flight by having the behaviour cast the next message to itself, so its peak measures only what is never released; it carries the ceiling, max_rss_mb = 40 MB: 508.9 MiB under the harness on 999943 (fails), 15.7 MiB with the fixed Mac build compiler/build/apple_silicon_mac/silica-compiler (passes). region_in_returned_record_released (H9, no actors; ~528 MB for 100,000 returned regions, ceiling 100 MB) is still open with the fixed build. No program output measures region memory (heap_used() does not count alloc_region blocks), so the leak checks are harness peak-RSS ceilings (host only; trials/README.md, “Peak memory ceiling”). The returned-record trial has no .ascomp yet. The two SD-7 trials moved to trials/message_regions_addition on 2026-10-22 with the SD-7 fix built (Mac 999942, pix and nix gen1); both pass there; a board run is still to do (trials/message_regions_open_addition/README.md).
  2. H1: unlocked canonical-arena bump and arena insert (design §1.3, §9.4). Atomic bump and compare-and-swap insert in the four runtimes. Write a hazard trial first; it fails before the fix and passes after. Status 2026-10-23: implemented and verified on the Mac, built on pix and nix with no compile errors (no trials run on the Linux compilers yet), ESP32-S3 mirror not built; staged hazard trials in trials/region_hazards_open_addition.
  3. H3: a let-bound aggregate passed by name to a call is not promoted. Staged trial wbt_map_tuple_value_escapes_via_let. Status 2026-10-23: implemented and verified on the Mac, built on pix and nix with no compile errors (no trials run on the Linux compilers yet), ESP32-S3 mirror not built; staged hazard trials in trials/region_hazards_open_addition.
  4. H4: a reply or state living in the replying actor’s arena dangles after that actor ends. BEES supervises every process and restarts constantly. The counted-storage stage that would have resolved this was removed (Q2 a), so this set needs the targeted stage 0 fix. Write the trial first to confirm it fails today. Status 2026-10-23: implemented and verified on the Mac, built on pix and nix with no compile errors (no trials run on the Linux compilers yet), ESP32-S3 mirror not built; staged hazard trials in trials/region_hazards_open_addition.
  5. H5: the hosted actor arena returns 0 on grow failure, and emit_alloc_region has no null check. Decided by Lee, 2026-10-22: in an actor the failure ends the actor with (:explicit, :region_alloc_failed), handled by its supervisor; abort 71 only in main. Status 2026-10-23: implemented and verified on the Mac, built on pix and nix with no compile errors (no trials run on the Linux compilers yet), ESP32-S3 mirror not built; staged hazard trials in trials/region_hazards_open_addition.
  6. Stage 8 / decision Q9: a bounds, invalid-size or allocation failure fails the actor and reaches its supervisor instead of aborting the process (design §13 stage 8, §15 Q9). Covers E2313, E2314 and the |bounds: question. Decided by Lee, 2026-10-23 (Q9 a): inside an actor an out-of-bounds buffer index, an invalid buffer size and a list-index failure terminate the actor with (:explicit, :buf_bounds), (:explicit, :buf_invalid) and (:explicit, :list_index); only in main do they remain runtime abort 71; the access is never performed. The |bounds:N SIR metadata was removed (nothing read it) and the run-time check stays for every index. Status 2026-10-23: implemented and verified on the Mac, built on pix and nix with no compile errors (no trials run on the Linux compilers yet), ESP32-S3 mirror not built; staged hazard trials in trials/region_hazards_open_addition.
  7. S-15: region release inside a living actor (BEES gap ledger S-15; evacuation copies live terms to a fresh region and releases the old one). Stages 2, 3, 4 and 5 of design §13 with the §18 move machinery, so that SD-7 passes. Rests on the decided Q1 (a), Q2 (a) and Q5 (a) (Lee, 2026-10-22). Messages that carry regions follow design §18.7 (Lee, 2026-10-22): regions are moved on send (Lee, 2026-10-23, Q18: a send copies by default and moves only on request, spelled move; the copy is made into a fresh owned region that then moves), dispatch-scoped in the receiver (dropped at behaviour return unless moved into the new state), and kept only by moving the whole region into the state (Q16 a) or by the compiler builtin copy_to(region, value), derived per type like recreate (Q15 a; no copy for a device_window or an atomic cell). This needs no counting (Q2 a). Under the standard, data_structure_redesign_requirements.md, structures are copied on send by default and moved on request, and the home and release of structure memory are chunk 15’s. Two failure paths the design had not covered belong to this item: (a) failed send: a cast, send or call to a dead actor returns actor_not_found and the runtime releases the moved region (Q17 a, decided 2026-10-22; a sender that needs the data copies first); (b) mailbox drain: the actor-end owner-list walk must include the regions of the actor’s unprocessed mailbox, so a crashed actor no longer leaks them. Also covered: a dead or timed-out caller’s reply regions, and the pattern that a sender who must survive the receiver’s death calls copy_to before sending. No use after an explicit move (Q18): it is E2301 to do any work with a region after sending it with an explicit move(...) (a plain send copies and the sender keeps its data), bare or contained in a record, tuple, list or closure, by name, field read or handle copy, on cast, send, call, reply and spawn state alike; the send_then_use_* error trials, which now apply to explicit move sends (bare region, record, tuple, list element, field read, later case branch, loop, recursion) are in design §18.6. Trials are listed in design §18.6 (not written).

Who does what (per the project’s silica-fable-use-reduction rules): the compiler and runtime changes in items 1 to 6 (atomic bump and insert, promotion of let-bound aggregates, the actor-end reply fix, the null checks, failure routing to the supervisor, the stages and move machinery) are compiler work for Fable. The ports and runs of item 0, the hazard and regression trials, builds, trial runs, golden refreshes and documentation are for lesser models.

Later paths

A new emitter’s first milestone has the same behaviours as the analogous pre-existing milestone, not Apple Silicon’s: a hosted path starts from the nearest existing hosted fixed point, and a bare-metal path starts from the nearest bare-metal one (bare-metal AArch64 takes the current ESP32-S3 board release, peek and poke included; a raw path has no fixed point). From there it works through the chunks. Hosted and bare metal stay parallel; smaller numbers mean sooner planned attention, not a guarantee. Among bare-metal rows in the same band, ESP32-S3 is listed first because a volunteer is driving it. If you enjoy ABIs, triples, link steps, CI on new hosts, or bringing up a small runtime on a board with no OS, pick a row and open a discussion or PR. See porting for OS-free targets.

Planned focus Strand Target Why it helps
1 Bare metal (OS-free, by chip) ESP32-S3 (Xtensa LX7) Brought up and running on a real board: ROM/startup, linker, runtime, two-core actors and drivers written in Silica. A volunteer is driving it, so it is listed first among the bare-metal rows; see its port status.
1 Bare metal (OS-free, by chip) AArch64 Real cores without a full OS; see memory effects on AArch64 / OS-free targets; ABI/runtime on a minimal environment.
2 Bare metal (OS-free, by chip) RISC-V (application-profile cores) Broad embedded/accelerator footprint; calling convention, linker/platform story, trials or hardware-in-the-loop.
3 Hosted (chip + OS) Windows (x86_64; AArch64 when there is demand) Lowers the barrier for contributors and teams on Windows workstations.
3 Bare metal (OS-free, by chip) Common MCU classes (e.g. 32-bit embedded) Longer tail of boards/ISAs; linker scripts, platform packages, minimal-runtime contract per profile.

Compiler-building tools

Tools for generating compiler code and coordinating work live under compiler/compiler-building-tools/.

For JSON-LD agent graphs, which files to use, and how they fit AI-assisted workflows, see compiler-building-tools/README.md.